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| dcdc converter digital sup i r buck IR38063 1 rev 3.8 may 26 , 2016 25 a single - input voltage, synchronous buck regulator with pmbus interface features description ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? o c IR38063 2 rev 3.8 may 26 , 2016 basic application figure 1 : typical application circuit figure 2 : performance curve pinout diagram figure 3 : IR38063 package (top view) 5 mm x 7mm p qfn b o o t v c c / l d o _ o u t f b c o m p s w v o p g o o d p g o o d r t / s y n c 5 . 5 v < v i n < 2 1 v p v i n v i n e n / f c c m v s n s r s + r s o r s - a d d r s c l / o c s e t s d a / i m o n s a l e r t / t m o n p g n d l g n d t r a c k _ e n p 1 v 8 v p IR38063 3 rev 3.8 may 26 , 2016 block diagram figure 4 : IR38063 simplified block diagram IR38063 4 rev 3.8 may 26 , 2016 pin descriptions pin # pin name pin description 1 pvin input voltage for power stage. bypass capacitors between pvin and pgnd should be connected very close to this pin and pgnd. 2 boot supply voltage for high side driver 3 track_en pull low to enable tracking function. leave floating to disable tracking function. 4 vp used for sequencing and tracking applications. leave open if not used. 5 vsns sense pin for ovp and pgood 6 fb inverting input to the error amplifier. this pin is connected directly to the output of the regulator or to the output of the remote sense amplifier, via resistor divider to set the output voltage and provide feedback to the error amplifier. 7 comp output of error amplifier. an external resistor and capacitor network is typically connected from this pin to fb to provide loop compensation. 8 rso remote sense amplifier output 9 rs - remote sense amplifier input. connect to ground at the load. 10 rs+ remote sense amplifier input. connect to output at the load. 11 pgood power good status pin. output is open drain. connect a pull up resistor from this pin to vcc. 12,25 pgnd power ground. this pin should be connected to the systems power ground plane. bypass capacitors between pvin and pgnd should be connected very close to the p vin pin (pin 1) and this pin. 13 lgnd signal ground for internal reference and control circuitry. 14 rt/sync in analog mode, u se an external resistor from this pin to gnd to set the switching frequency . the resistor should be placed very close to the pin. this pin can also be used for external synchronization. no resistor is used in digital mode. 15 en/fccm enable pin to turn on and off the ic . in analog mode , also ser ves as a mode pin, forcing the converter to operate in ccm when pulled to< 3.1v . 16 addr sets pmbus address for the device; should be floated if digital communication is not needed. 17 salert /tmon smbus alert line; pin provides a voltage proportional to the junction temperature if digital communication is not needed. 18 sda/imon smbus data serial input/output line; pin provides a voltage proportional to the output current if digital communication is not needed. 19 scl/ ocset smbus clock line; used to set oc thresholds if digital communication is not needed. 20 p1v8 this is the supply for the digital circuits; bypass with a 2.2uf capacitor to lgnd or pgnd 21 vin input voltage for ldo. 22 vcc bias voltage for ic and driver section, output of ldo. add 10 uf bypass cap from this pin to pgnd. 23,26 nc nc 24 sw switch node. this pin is connected to the output inductor. IR38063 5 rev 3.8 may 26 , 2016 absolute maximum rat ings stresses beyond th e se listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. pvin, vin - 0.3v to 25v vcc - 0.3v to 6v p1v8 - 0.3v to 2 v sw - 0.3v to 25v (dc), - 4v to 25v (ac, 100ns) boot - 0.3v to 31 v pgd, other input/output pins - 0.3v to 6v (note 1) boot to sw - 0.3v to 6v (dc), - 0.3v to 6.5v (ac, 100ns) pgnd to gnd, rs - to gnd - 0.3v to + 0.3v thermal information junction to case thermal resistance ? jc - top 30 o c/w junction to ambient thermal resistance ? ja 13 . 8 o c/w junction to pcb thermal resistance ? j - pcb 2.05 o c/w storage temperature range - 55c to 150c junction temperature range - 40c to 150c (voltages referenced to gnd unless otherwise specified) note 1: must not exceed 6v. IR38063 6 rev 3.8 may 26 , 2016 electrical specifica tions recommended operatin g conditions symbol definition min max units pvin input bus voltage 1.2 21* v vin ldo supply voltage 5.5 21 vcc ldo output/bias supply voltage 4.5 5. 5 boot to sw high side driver gate voltage 4.5 5.5 v o output voltage 0.5 0.875*pv in i o output current 0 25 a fs switching frequency 225 1650 khz t j junction temperature - 40 125 c * sw node must not exceed 25v electrical character istics unless otherwise specified, these specification apply over, 1.5v < pvin < 21v, 4.5v < vcc < 5.5, 0 ? c < t j < 125 ? c. typical values are specified at t a = 25 ? c. parameter symbol conditions min typ max unit mosfet r ds(on) top switch rds(on)_top v boot C v sw = 5v, i d = 25a, tj = 25c 2.7 4 5.6 m? bottom switch rds(on)_bot vcc =5v, i d = 25a, tj = 25c 1.11 1.58 2.05 reference voltage accuracy 0 0 c IR38063 10 rev 3.8 may 26 , 2016 parameter symbol conditions min typ max unit power good high threshold rising delay tpdly vsns rising, vsns > power_good_high 0 ms power good low threshold falling delay vpg_low_dly vsns falling, vsns < power_good_low 150 1 75 200 us tracker comparator upper threshold vpg(tracker_ upper) vp rising, vout_scale_loop=1, track_en low, vsns=vp 0.38 0.4 0.42 v tracker comparator lower threshold vpg(tracker_ lower) vp falling, vout_scale_loop=1, track_en low, vsns=vp 0.28 0.3 0.32 v pgood voltage low pg (voltage) i pgood = - 5ma 0.5 v over voltage protection (ovp) ovp trip threshold ovp (trip) vsns rising, vout_scale_loop=1, track_en floating, vdac1=0.5v 115 121 125 %vdac1 vsns rising, vout_scale_loop=1, track_en low, vp=0.5v 115 120 125 %vp ovp comparator hysteresis ovp (hyst) vsns falling, vout_scale_loop=1, track_en floating, vdac1=0.5v 2.5 4. 5 5.8 %ovp (trip) vsns falling, vout_scale_loop=1, track_en low, vp=0.5v 2.5 4. 5 5.8 %ovp (trip) ovp fault prop delay ovp (delay) vsns rising , vsns - ovp(trip)>200 mv 2 00 n s over - current protection oc trip current i trip oc limit=33a, vcc = 5. 05 v , t j =25 0 c 30 33 36 a oc limit=27a, vcc = 5.05 v , t j =25 0 c 2 4. 5 2 7 29 .5 a oc limit=21a , vcc = 5. 05 v , t j =25 0 c 18.3 21 23.7 a ocset current temperature coefficient ocset(temp) - 40 0 c to 125 0 c, vcc= 5.05 v, note 2 59 00 ppm/c hiccup blanking time tblk_hiccup note 2 20 ms thermal shutdown thermal shutdown note 2 145 c hysteresis note 2 25 c input over - voltage protection pvin overvoltage threshold pvin ov 22 2 3.7 25 v IR38063 11 rev 3.8 may 26 , 2016 parameter symbol conditions min typ max unit pvin overvoltage hysteresis pvin ov hyst 2.4 v monitoring and reporting bus speed 1 100 400 khz iout & vout filter 78 hz iout & vout update rate 31.2 5 khz vin & temperature filter 78 hz vin & temperature update rate 31.2 5 khz output voltage reporting resolution n vout note 2 1/256 v lowest reported vout vomon_low vsns=0v 0 v highest reported vout vomon_high vout_scale_loop=1, vsns=3.3v 3.3 v vout_scale_loop=0.5, vsns=3.3v 6.6 v vout_scale_loop=0.25, vsns=3.3v 13.2 v vout_scale_loop=0.125 , vsns=3.3v 26.4 v vout reporting accuracy 0 0 c to 8 5 0 c, 4.5v IR38063 14 rev 3.8 may 26 , 2016 t ypical application d iagram s figure 5 : using the internal ldo , digital mode , vo < 2.555v figure 6 : using the internal ldo, digital mode , vo > 2.555v b o o t v c c / l d o _ o u t f b c o m p s w v o p g o o d p g o o d r t / s y n c 5 . 5 v < v i n < 2 1 v p v i n v i n e n / f c c m v s n s r s + r s o r s - a d d r s c l / o c s e t s d a / i m o n s a l e r t / t m o n p g n d l g n d t r a c k _ e n p 1 v 8 v p b o o t v c c / l d o _ o u t f b c o m p s w v o p g o o d p g o o d r t / s y n c 5 . 5 v < v i n < 2 1 v p v i n v i n e n / f c c m v s n s r s + r s o r s - a d d r s c l / o c s e t s d a / i m o n s a l e r t / t m o n p g n d l g n d t r a c k _ e n p 1 v 8 v p IR38063 15 rev 3.8 may 26 , 2016 t ypical application d iagram s figure 7 : using the internal ldo, analog mode figure 8 : using external vcc, digital mode , vo<2.555v b o o t v c c / l d o _ o u t f b c o m p s w v o p g o o d p g o o d r t / s y n c 5 . 5 v < v i n < 2 1 v p v i n v i n e n / f c c m v s n s r s + r s o r s - a d d r s c l / o c s e t s d a / i m o n s a l e r t / t m o n p g n d l g n d t r a c k _ e n p 1 v 8 v p b o o t v c c / l d o _ o u t f b c o m p s w v o p g o o d p g o o d r t / s y n c 1 . 2 v < p v i n < 2 1 v p v i n v i n e n / f c c m v s n s r s + r s o r s - a d d r s c l / o c s e t s d a / i m o n s a l e r t / t m o n p g n d l g n d t r a c k _ e n p 1 v 8 v p v c c = 5 v IR38063 16 rev 3.8 may 26 , 2016 t ypical application d iagram s figure 9 : single 5v application, digital mode , vo<2.555v figure 10 : using the internal ldo, digital mode, tracking mode b o o t v c c / l d o _ o u t f b c o m p s w v o p g o o d p g o o d r t / s y n c p v i n = v i n = v c c = 5 v p v i n v i n e n / f c c m v s n s r s + r s o r s - a d d r s c l / o c s e t s d a / i m o n s a l e r t / t m o n p g n d l g n d t r a c k _ e n p 1 v 8 v p b o o t v c c / l d o _ o u t f b c o m p s w v o p g o o d p g o o d r t / s y n c 5 . 5 v < v i n < 2 1 v p v i n v i n e n / f c c m v s n s r s + r s o r s - a d d r s c l / o c s e t s d a / i m o n s a l e r t / t m o n p g n d l g n d t r a c k _ e n p 1 v 8 v p IR38063 17 rev 3.8 may 26 , 2016 typical operating ch aracteristics ( - 40c to +125c) IR38063 18 rev 3.8 may 26 , 2016 typical operating ch aracteristics ( - 40c to +125c) IR38063 19 rev 3.8 may 26 , 2016 typical operating ch aracteristics ( - 40c to +125c) IR38063 20 rev 3.8 may 26 , 2016 typical operating ch aracteristics ( - 40c to +125c) IR38063 21 rev 3.8 may 26 , 2016 typical efficiency a nd power loss curves pvin = vin = 12v, vcc = internal ldo, io=0 - 25a, fs= 600khz, room temperature, no air flow. note that the losses of the inductor, input and output capacitors are also considered in the efficiency and power loss curves. the table below shows the indicator used for each of the output voltages in the efficiency measurement. vout (v) lout (uh) p/n dcr (m) 0.6 0. 15 hcb178380d - 151 (delta) 0.15 0.8 0.15 hcb178380d - 151 (delta) 0.15 1 0.15 hcb178380d - 151 (delta) 0.15 1.2 0.215 pcdc1008 - r215emo (cyntec) 0.29 1.5 0.215 pcdc1008 - r215emo (cyntec) 0.29 1.8 0.215 pcdc1008 - r215emo (cyntec) 0.29 2.5 0.3 59pr987n (vitec) 0.29 3.3 0.47 we - hcm 744 309 047 (wurth) 0.15 5 0.47 we - hcm 744 309 047 (wurth) 0.15 IR38063 22 rev 3.8 may 26 , 2016 typical efficiency a nd power loss curves pvin = vin = vcc = 5v, io=0 - 2 5a, fs= 600khz, room temperature, no air flow. note that the losses of the inductor, input and output capacitors are also considered in the efficiency and power loss curves. the table below shows the indicator used for each o f the output voltages in the efficiency measurement. vout (v) lout (uh) p/n dcr (m) 0.6 0.15 hcb178380d - 151 (delta) 0.15 0.8 0.15 hcb178380d - 151 (delta) 0.15 1 0.15 hcb178380d - 151 (delta) 0.15 1.2 0.15 hcb178380d - 151 (delta) 0.15 1.5 0.15 hcb178380d - 151 (delta) 0.15 1.8 0.215 pcdc1008 - r215emo (cyntec) 0.29 2.5 0.215 pcdc1008 - r215emo (cyntec) 0.29 3.3 0.215 pcdc1008 - r215emo (cyntec) 0.29 IR38063 23 rev 3.8 may 26 , 2016 theory of operation description the IR38063 is a 25a synchronous buck regulator with a selectable digital interface and a n externally compensated fast, analog, pwm voltage mode control scheme to provide good noise immunity as well as fast dynamic response in a wide variety of applications. at the sa me time, enabling the digital pmbus interface allows complete configurability of output setting and fault functions, as well as telemetry. the switching frequency is programmable from 166 khz to 1.5mhz and provides the capability of optimizing the design in terms of size and performance. IR38063 provides precisely regulated output voltage from 0.5v to 0.8 75 * p vin programmed via two external resistors or digitally through pmbus commands. the IR38063 operates with an internal bias supply (ldo) , typically 5.2v . this allows operation with a single supply. the output of this ldo is brought out at the vcc pin and may be bypassed to the system power ground with a 10 uf decoupling capacitor. the vcc pin may also be connected to the vin pin, and an external vcc suppl y between 4.5v and 5.5v may be used, allowing an extended operating bus voltage (pvin) range from 1. 2 v to 21v . the device utilizes the on - resistance of the low side mosfet (sync hronous mosfet ) as current sense element. this method enhances the converters efficiency and reduces cost by eliminating the need for external current sense resistor. IR38063 includes two low r ds(on) mosfets using irs hexfet technology. these are specifically designed for high efficiency applications. device power - up and initiali zation during the power - up sequence, when vin is brought up, the internal ldo converts it to a regulated 5.2v at vcc. there is another ldo which further converts this down to 1.8v to supply the internal digital circuitry. an under - voltage lockout circuit m onitors the voltage of v cc pin and the p1v8 pin, and holds the power - on - reset (por) low until these voltages exceed their thresholds and the internal 48 mhz oscillator is stable. when the device comes out of reset, it initializes a multiple times programma ble memory (mtp) load cycle, where the contents of the mtp are loaded into the working registers. once the registers are loaded from mtp, the designer can use pmbus commands to re - configure the various parameters to suit the specific vr design requirements if desired, irrespective of the status of enable. in the default configuration, power conversion is enabled only when the en/fccm pin voltage exceeds its undervoltage threshold, the pvin bus voltage exceeds its undervoltage threshold, the contents of the mtp have been fully loaded into the working registers and the device address has been read. the initialization se quence is shown in figure figure 11 . IR38063 provides additional options to enable the device power conversion through software and these options may be configured to override the default by using the i2c interface or pmbus, if used in digital mode. for further details see the un0060 ir3806x pmbus commandset user note . figure 11 : IR38063 initialization sequence analog and digital mode operati on the IR38063 has 2 7 - bit registers that are used to set the base i2c address and base pmbus addr ess of the device, as shown below in table 1 . p v i n = v i n v c c p 1 v 8 u v o k c l k r d y p o r i n i t i a l i z a t i o n d o n e e n a b l e v o u t IR38063 24 rev 3.8 may 26 , 2016 table 1 : registers used to set device base address register description i2c_address[6:0] the chip i2c address. an address of 0 will disable communication pmbus_address[6:0] the chip pmbus address. an address of 0 will disable communication. in addition, a resistor may be connected between the addr and lgnd pins to set an offset from the default preconfigured i2c address (0x10) /pmbus address (0x40) in the mtp. up to 16 different offsets can be set, allowing 16 IR38063 devices with unique addresses in a single system. this offset, and hence, the device address, is read by the internal 10 bit adc during the initialization sequence . table 2 below provides the resistor values needed to set the 16 offsets from the base address. table 2 : address offset vs. external resistor( r addr ) addr resistor (ohm) address offset 0 +0 1050 +1 1540 +2 2050 +3 2610 +4 3240 +5 3830 +6 4530 +7 5230 +8 6040 +9 6980 +10 7870 +11 8870 +12 9760 +13 10700 +14 11800 +15 the device will then respond to i2c/pmbus commands sent to this address. this mode in which digital communication to and from the device is allowed following the mtp load sequence is referred to as the digital mode of operation. however, if the addr pin is left floating, the IR38063 disables digital communication and will not respond to commands sent over the bus. in fact, the 3 pins used for digital communication are dual purpose pins which get reconfigured for analog applications if addr is left floating. hence, in the analog mode, the default configuration parameters loaded in to the working registers from the mtp during the initia lization sequence cannot be modified on the fly, and the device can be operated similar to an analog only supirbuck such as ir3847. bus voltage uvlo in the analog mode of operation or with the default configuration, i f the input to the enable pin is derive d from the bus voltage by a suitably programmed resistive divider, it can be ensured that the IR38063 does not turn on until the bus voltage reaches the desired level as shown in figure 12 . only after the bus voltage r eaches or exceeds this level and voltage at the enable pin exceed s its threshold (typically 1.2v) IR38063 will be enabled. therefore, in addition to being a logic input pin to enable the IR38063 , the enable feature, with its precise threshold, also allows the user to override the default 1 v under - voltage lockout for the bus voltage ( pvin ). this is desirable particularly for high output voltage applications, where we might want the IR38063 to be disabled at least until pvin exceeds t he desired output voltage level . alternatively, the default 1 v pvin uvlo threshold may be reconfigured/overridden using the vin_on and vin_off pmbus commands. it should be noted that while the input voltage is also fed to an adc through a 21:1 internal resistive divider, t he digitized input voltage is used only for the purposes of reporting the input voltage through the read_vin pmbus command and has no impact on the bus voltage uvlo, input overvoltage faults and input undervoltage warnings, all of which are implemented by using analog comparators to compare the input voltage to the corresponding thresholds IR38063 25 rev 3.8 may 26 , 2016 programmed by the pmbus commands vin_on, vin_off, vin_ov_fault_limit and vin_uv_warn_limit respectively. the bus voltage reading as reported by read_vin has no effect on the input feedforward function either. figure 12 : normal start up, device turns on when the bus voltage reaches 10.2v a resistor divider is used at en pin from pvin to turn on the device at 10.2v. figure 13 : recommended startup for normal operation figure 14 : recommended startup for sequencing operation (ratiometric or simultaneous) figure 15 : recommended startup for memory tracking operation ( ddr - vtt ) figure 13 shows the recommended start up sequence for the normal (non - tracking, non - sequencing) operation of IR38063 , when enable is used as logic input. in this operating mode track_en is left floating. figure 14 shows the recommended startup sequence for sequenced operation of IR38063 with enable used as logic input. f or this mode of op eration, track_en is left floating. figure 15 shows the recommended startup sequence for tracking operation of IR38063 with enable used as logic input. for this mode of operation, track_en should be connected to lgnd . pre - bias startup IR38063 is able to start up into pre - charged output, which prevents oscillation and disturbances of the output v oltage. the output starts in asynchronous fashion and keeps the synchronous mosfet (sync fet) off until the first gate signal for control mosfet (ctrl fet) is generated. figure 16 shows a typical pre - bias condition at start up. the s ync fet always starts with a narrow pulse width (12.5% of a switching period) and gradually increases its duty cycle with a step of 12.5% , with 16 cycles at each step, until it reaches the steady state value. figure 17 shows the series of 16x8 startup pulses . v c c p v i n d a c 2 ( r e f e r e n c e d a c ) e n > 1 . 2 v 1 . 2 v e n _ u v l o _ s t a r t 1 0 . 2 v 1 2 v 1 v v c c p v i n = v i n e n > 1 . 2 v v p d a c 2 ( r e f e r e n c e d a c ) v c c p v i n = v i n e n > 1 . 2 v v p d a c 2 ( r e f e r e n c e d a c ) v c c p v i n = v i n e n > 1 . 2 v v p t r a c k _ e n 0 v d a c 2 ( r e f e r e n c e d a c ) IR38063 26 rev 3.8 may 26 , 2016 figure 16 : pre - bias startup figure 17 : pre - bias startup pulses soft - start ( reference dac ramp) IR38063 ha s an internal soft starting dac to control the output voltage rise and to limit the current surge at the start - up. in the default configuration and in analog mode, t o ensure correct start - up, the dac sequence initiates only after power conversion is enable d when the en/fccm pin voltage exceeds its undervoltage threshold, the pvin bus voltage exceeds its undervoltage threshold and the contents of the mtp have been fully loaded into the working registers. in analog mode and in the default configuration, t he r eference dac signal linearly rises to 0.5v in 2 ms. figure 18 shows the waveforms during soft start in digital mode, the reference dac soft - start may be delayed from time power conversion is enabled. the range for this programmable delay is 0ms to 127 ms, and the resolution is 1 ms. further, the soft start time may be configured from 1ms to 127 ms with 1 ms resolution. for more details on the pmbus commands ton_delay and ton_rise used to program the startup sequence, please see the un0060 ir3806x pmbus commandset user note . note however, that a shorter ton_rise can lead to a slight overshoot on the output voltage during startup and it i s recommended that the system designer should verify in the actual design that the selected rise time keeps the overshoot within limits acceptable to the system. figure 18 : dac2 (vref) soft start during the startup sequence the over - current protection (ocp) and over - voltage protection (ovp) are active to protect the device for any short circuit or over voltage condition. operating frequency in the analog mode, t he switchi ng frequency can be progra mmed b etween 306 khz C 1500khz by connecting an external resistor from r t pin to lgnd . this frequency is set during the initialization sequence, when the 10 bit adc reads the voltage at the rt pin. it should be noted that after the initialization sequence i s complete, the adc no longer reads the voltage at the adc pin, so changing the resistor on the fly after initialization will not affect the switching frequency . table 3 tabulates the oscillator frequency versus r t . table 3 : switching frequency ( f s ) vs. external resistor( r t ) r t resistor (ohm) f s (khz) 0 306 1050 356 1540 400 vo [ v ] [ time ] pre - bias voltage ... ... ... hdrv ... ... ... 16 end of pb ldrv 12 . 5 % 25 % 87 . 5 % 16 ... ... ... ... r e f e r e n c e d a c v o u t t 1 0 . 5 v i n t e r n a l e n a b l e t 3 t 2 t o n _ d e l a y t o n _ r i s e IR38063 27 rev 3.8 may 26 , 2016 2050 444 2610 500 3240 550 3830 600 4530 706 5230 750 6040 800 6980 923 7870 1000 8870 1091 9760 1200 10700 1333 11800 1500 in the digital mode, the default switching frequency is configured to be 60 7 khz, and is programmable from 250 khz to 1500 khz . the user can override this using the frequency_switch pmbus command. in the digital mode of operation no resistor is used or needed on the r t / sync pin. external synchronization IR38063 incorporates an internal phase lock loop (pll) circuit which enables synchronization of the internal oscillator to an external clock. this function is important to avoid sub - harmonic oscillations due to beat frequency for embedded systems when multiple po int - of - load (pol) regulators are used. a multi - function pin, rt/sync, is used to connect the external clock. in the analog mode, if the external clock is applied before the initialization sequence is done , the internal adc cannot read the value of the rt r esistor and hence, for proper operation, it is mandatory that the external clock remains applied. if the synchronization clock is then lost after initialization, the IR38063 will treat this as a symptom of a failure in the system and disable power conversi on. therefore, for such applications, where the switching frequency is always determined by an external synchronization clock, the rt/sync pin can be connected to the external clock signal solely and no other resistor is needed. if the external clock is ap plied after the initialization sequence, the IR38063 treats this as an application where the converter switching frequency needs to toggle between the external clock frequency and the internal free - running frequency, and in the analog mode, an external res istor from rt/sync pin to lgnd is required to set the free - running frequency. in the digital mode, the resistor is not needed because the free running frequency is set in an internal register. when an external clock is applied to rt/sync pin after the con verter runs in steady state with its free - running frequency, a transition from the free - running frequency to the external clock frequency will happen. this transition is to gradually make the actual switching frequency equal to the external clock frequency , no matter which one is higher. w hen the external clock signal is removed from rt/sync pin, the switching frequency is also changed to free - running gradually. figure 19 : timing diagram for synchronization to the external clock (fs1>fs2 or fs1 IR38063 29 rev 3.8 may 26 , 2016 the inductor value, input voltage , output voltage and the frequency of operation. ( 1 ) i ocp = dc current limit hiccup point i limit = current limit valley point i = inductor ripple current figure 21 : timing diagram for current limit hiccup in the default c onfiguration and in analog mode, if the o vercurrent detection trips the ocp comparator, the IR38063 goes into a hiccup mode. the hiccup is performed by de - asserting the internal enable signal to the analog and power conversion circuitry and holding it low for 20 ms . following this, the ocp signal resets and the converter recovers. after every hiccup cycle, the converter stays in this mode until the overload or short circuit is removed. this behavior is shown in figure 21 . note that the IR38063 allows the user to override the default overcurrent threshold using the pmbus command iout_oc_fault_limit. also, using the pmbus command iout_oc_fault_response, the part may be configured to respond to an overcurrent fault in one of five ways 1) constant current operation through pulse by pulse current limiting 2) pulse by pulse current limiting for a programmed number of switching cycles (8 to 64 cycles, in 8 cycle resolution) followed by a latched shutdown. 3) pulse by pulse c urrent limiting for a programmed number ( 8 to 64 cycles, in 8 cycle resolution) of switching cycles followed by hiccup. 4) immediate latched shutdown 5) immediate hiccup. the pulse - by - pulse or constant current limiting mechanism is briefly explained be low . figure 22 : pulse by pulse current limiting for 8 cycles, followed by hiccup. in figure 22 above, with the overcurrent response set to pulse - by - pulse current limiting for 8 cycles followed by hiccup, the converter is operating at d<0.125 when the overcurrent condition occurs. in such a case, no duty cycle limiting is applied. figure 23 : constant current limiting. figure 23 depicts a case where the overcurrent condition happens when the converter is operating at d>0.5 and the overcurrent response has been set 2 i i i limit ocp ? ? ? 0 i l 0 h d r v c u r r e n t l i m i t 0 l d r v . . . . . . 0 p g o o d h i c c u p t b l k _ h i c c u p 2 0 m s 0 i l 0 h d r v f s i o u t _ o c _ f a u l t _ l i m i t 0 0 c l k l d r v 2 0 m s i n t e r n a l e n a b l e o c p h i g h 1 2 3 4 5 6 7 8 0 il 0 hdrv fs io ut _ oc _ fa ult _ lim it 0 0 clk ldrv internal enable ocp high 1 2 3 4 5 6 7 8 9 10 ... 11 IR38063 30 rev 3.8 may 26 , 2016 to constant current operation through pulse by pulse current limiting. in such a case, after 3 consecutive overcurrent cycles are recognized, the pulse width is dropped such that d=0.5 and then after 3 more consecutive ocp cycles, to 0.25 and then finally to 0.125 at which i t keeps running until the total ocp count reaches the programmed maximum following which the part enters hiccup mode. conversely, when the overcurrent condition disappears, the pulse width is restored to its nominal value gradually, by a similar mechanism in reverse; every sequence of 4 consecutive cycles in which the current is below the overcurrent threshold doubles the duty cycle, so that d goes from 0.125 to 0.25, then to 0.5 and finally to its nominal value. die temperature sens ing, telemetry and t hermal shutdown IR38063 uses on die temperature sensing for accurate temperature reporting and over temperature detection . the read_temeprature pmbus command reports this temperature in 1 0 c resolution. the trip threshold is set by default to 145 o c. the def ault over temperature response of the IR38063 (also the response in analog mode) is to inhibit power conversion while the fault is present, followed by automatic restart after the fault condition is cleared. hence, in the default configuration, w hen trip t hresho ld is exceeded, the internal enable signal to the power conversion circuitry is de - asserted, turning off both mosfets. automatic restart is initiated when the sensed temperature drops within the operating range. there is a 25 o c hysteresis in the ther mal shutdown threshold. the default overtemperature threshold as well as overtemperature response may be re - configured or overridden using the ot_fault_limit and ot_fault_response pmbus commands respectively. the devices support three types of responses to an over - temperature fault: 1) ignore 2) inhibit when over temperature condition exists and auto - restart when over temperature condition disappears 3) latched shutdown. remote voltage sensi ng true differential remote sensing in the feedback loop is crit ical to high current applications where the output voltage across the load may differ from the output voltage measured locally across an output capacitor at the output inductor, and to applications that require die voltage sensing. the rs+ and rs - pins of the IR38063 form the inputs to a remote sense differential amplifier with high speed, low input offset and low input bias current which ensure accurate voltage sensing and fast transient response in such applications. the input range for the differential a mplifier is limited to 1.5v below the vcc rail. therefore, for applications in which the output voltage is more than 3v, it is recommended to use local sensing, or if remote sensing is a must, then the output voltage between the rs+ and rs - pins must be di vided down to less than 3v using a resistive voltage divider. practically, since designs for output voltage greater than 2.555v require the use of a resistive divider anyway, it is recommended that this divider be placed at the input of the remote sense am plifier. please note, however, that this modifies the open loop transfer function and requires a change in the compensation network to optimally stabilize the loop. feed - forward feed - forward (f.f.) is an important feature, because it can keep the converter stable and preserve its load transient performance when p vin varies over a wide range . the pwm ramp amplitude (vramp) is proportionally changed with p vin to maintain p vin/vramp almost constant throughout p vin variation range (as shown in figure 24 ). thus, the control loop bandwidth and phase margin can be maintained constant. feed - forward function can also minimize impact on output voltage from fast p vin change. the feedforward is disa bled for pvin<4.7v. hence, for pvin<4.7v, a re - calculation of control loop parameters is needed for re - compensation. IR38063 31 rev 3.8 may 26 , 2016 figure 24 : timing diagram for feed - forward (f.f.) function light load efficienc y enhancement ( aot ) the IR38063 implements an adaptive on time control or aot scheme to improve light load efficiency. it is based on a cot (constant on time) control scheme with some novel advancements that make the on - time during diode emulation adaptive a nd dependent upon the pulse width in constant frequency operation. this allows the scheme to be combined with a pwm scheme, while providing relatively smooth transition between the two modes of operation. in other words, the switching regulator can operat e in aot mode at light loads and automatically switch to pwm at medium and heavy loads and vice versa. therefore, the regulator will benefit from the high efficiency of the aot mode at light loads , and from the constant frequency and fast transient respons e of the pwm at medium to heavy loads. in order to enable this light load efficiency enhancement mode in analog operation, the voltage at the en/fccm pin needs to be kept above 4v. in digital mode, a mfr_specific pmbus command (mfr_fccm) can be used to ena ble aot operation at light load. shortly after the reference voltage has finished ramping up, an internal circuit which is called the calibration circuit starts operation. it samples the comp voltage (output of the error amplifier), digitizes it and stor es it in a register. there is a dac which converts the value of this register to an analog voltage which is equal to the sampled comp voltage. at this time, the regulator is ready to enter aot mode if the load condition is appropriate. if the load is so lo w that the inductor current becomes negative before the next sw pulse, the operation can be switched to aot mode. the condition to enter aot is the occurrence of 8 consecutive inductor current zero crossings in eight consecutive swi tching cycles. if this h appens, operation is switched to aot mode as shown in figure 25 . the inductor current is sensed using the rds_on of the sync - fet and no direct inductor current measuring is required. in aot mode, just like cot operation, pulses with constant width are generated and diode emulation is utilized. this means that a pulse is generated and ldrv is held on until the inductor current becomes zero. then both hdrv and ldrv remain off until the voltage of the sense pin comes down and reaches the reference voltage. at this moment the next pulse is generated. the sense pin is conne cted to the output voltage by a resistor divider which has the same ratio as the voltage divider which is connected to the feedback pin (fb). figure 25 : timing diagram for reduced switching frequency a nd diode emulation in light load condition ( aot mode) when the load increases beyond a certain value, the control is switched back to pwm through either of the following two mechanisms: - if due to the increase in load, the output voltage drops to 95% of the reference voltage. - if vsense remains below the reference voltage for 3 consecutive inductor current zero - cross events 0 0 p v i n p w m r a m p 1 2 v r a m p o f f s e t 2 1 v 5 v 1 2 v hdrv 0 0 ldrv 0 sw 0 il ton 0 vout ... ... ... ... ... ... ... ... 1 / fs reduced switching frequency 8 / fs delay diode emulation IR38063 32 rev 3.8 may 26 , 2016 it is worth mentioning that in aot mode, when vsense comes down to reference voltage level, a new pulse in generated only if th e inductor current is already zero. if at this time the inductor current (sensed on the sync - fet) is still positive, the new pulse generation is postponed till the current decays to zero. the second condition mentioned above usually happens when the load i s gradually increased. it should be noted that in tracking mode, aot operation is disabled and the IR38063 can only operate in continuous conduction mode even at light loads. in digital mode, if the output voltage and hence the reference voltage is comman ded to a different voltage, aot is disabled during the transition. it is enabled only after reference voltage finishes its ramp (up or down) and the calibration circuit has sampled and held the new comp voltage. output voltage track ing and sequencing ir38 063 can accommodate user programmable tracking and/or sequencing options using vp, track_en , enable, and power good pins. t he error - amplifier (e/a) has t wo non - inverting inputs. ideally, the input with the lowest voltage is used for re gulating the output voltage and the other input is ignored. in pra ctice the voltage of the other input should be about 200mv greater than the low - voltage input so that its effects can completely be ignored. vp and track_enable are internally biased to 5v via a high impedance path. for normal operation, vp and track_enable are left floating. therefore, in normal operating condition, after enable goes high, dac2 ramps up the output voltage until vfb (voltage of feedback/fb pin) reaches about 0. 5 v. tracking - mode operation is achieved by connecting track_en to lgnd . in tracking mode, vfb always follows vp which means vout is always proportional to vp voltage (typical for ddr/vtt rail applications). the effective vp variation range is 0v~ 2. 555v . in sequencing mode of operation (simultaneous or ratiometric), track_en is left floating and vp is kept to ground level until dac2 signal reaches the final value. then vp is ramped up and vfb follows vp. when vp> dac2 (0.5v in anal og mode or default configuration) the error - amplifier switches to dac2 and the output voltage is regulated with dac2 . the final vp voltage after seq uencing startup should between 0.7 v ~ 5v . figure 26 : application circuit for simultaneous and ratiometric sequencing tracking and sequencing operations can be implemented to be simultaneous or ratiometric (ref er to figure 27 and figure 28 ). figure 26 shows typical circuit configuration for sequencing operation. with this power - up configuration, the voltage at the vp pin of the slave reaches 0. 5 v before the fb p in of the master. if r e /r f =r c /r d , simultaneous startup is achieved. that is, the output voltage of the slave follows that of the master until the voltage at the vp pin of the slave reaches 0. 5 v. after the voltage at the vp pin of the slave exceeds 0. 5 v, the internal 0 . 5 v reference of the slave dictates its output voltage. in reality the regulation gradua lly shifts from b o o t v c c f b c o m p g n d p g n d s w v o 1 ( m a s t e r ) p g o o d p g o o d r t / s y n c 5 . 5 v < v i n < 2 1 v p v i n v i n v s n s s c l / o c s e t r s + r s o r s - t r a c k _ e n v p e n / f c c m r a r b s d a / i m o n s a l e r t / t m o n a d d r b o o t v c c f b c o m p p g n d s w v o 2 ( s l a v e ) p g o o d p g o o d r t / s y n c 5 . 5 v < v i n < 2 1 v p v i n v i n v s n s s c l / o c s e t r s + r s o r s - v p e n / f c c m v o 1 ( m a s t e r ) r e r f r d r c g n d t r a c k _ e n s d a / i m o n s a l e r t / t m o n a d d r IR38063 33 rev 3.8 may 26 , 2016 vp to internal dac2 . the circuit shown in figure 26 can also be used for simultaneous or ratiometric tracking operation if the track_en pin of the slave is connected to lgnd . table 4 summarizes the required condi tions to achieve simultaneous / ratiometric tracking or sequencing operations. figure 27 : typical waveforms for sequencing mode of operation: (a) simultaneous, (b) ratiometric figure 28 : typical waveforms in tracking mode of operation: (a) simultaneous, (b) ratiometric table 4 : required conditions for simultaneous / ratiometric tracking and sequencing ( figure 26 ) operating mode track_e nable (slave) vp required condition normal floating floating D (non - sequencing, non - tracking) simultaneous sequencing floating ramp up from 0v r a /r b >r e / r f =r c /r d ratiometric sequencing floating ramp up from 0v r a /r b >r e / r f >r c /r d simultaneous tracking 0v ramp up from 0v r e /r f =r c /r d ratiometric tracking 0v ramp up from 0v r e /r f >r c /r d track_en this pin is used to choose between tracking or non - tracking mode of operation. to enable operation in tracking mode, this pin must be tied to lgnd. if left floating, this pin internally pulls up to vcc and selects non - tracking or sequencing mode of operation. output voltage sensi ng , telemetry and faults in the IR38063 , the voltage sense and regulation circuits are decoupled, enabling ease of testing as well as redundancy. in order to do this, IR38063 uses the sense voltage at the dedicated vsns pin for output voltage reporting (in 1/256 v resolution, using the read_vout pmbus command) as well as for power good detection and output overvoltage protection. power good detection and output overvoltage detection rely on fast analog comparator circuits, whereas overvoltage warnings as we ll as undervoltage faults and warnings rely on comparing the digitized vsns to the corresponding thresholds programmed using pmbus commands vout_ov_warn_limit,vout_uv_fault_limit and vout_uv_warn_limit respectively. power good output the vsns voltage is a n input to the window comparator with default upper and lower thresholds of 0.45v and 0.42v respectively. pgood signal is high whenever vsns voltage is within the pgood v c c r e f e r e n c e d a c = 0 . 5 v 1 . 2 v s o f t s t a r t ( s l a v e ) e n a b l e ( s l a v e ) v o 1 ( m a s t e r ) v o 2 ( s l a v e ) ( a ) v o 1 ( m a s t e r ) v o 2 ( s l a v e ) ( b ) v c c t r a c k _ e n = 0 v ( s l a v e ) 1 . 2 v s o f t s t a r t ( s l a v e ) e n a b l e ( s l a v e ) v o 1 ( m a s t e r ) v o 2 ( s l a v e ) ( a ) v o 1 ( m a s t e r ) v o 2 ( s l a v e ) ( b ) IR38063 34 rev 3.8 may 26 , 2016 comparator window thresholds. the pgood pin is open drain and it needs to be externally pulled high. high state indicates that output is in regulation. it should be noted, that in digital mode, the power good thresholds may be changed through the power_good_on and power_good_off commands, which set the rising and falling pgood thresholds res pectively. however, when no resistive divider is used, such as for output voltages lower than 2.555v, the power good thresholds must be programmed to within 630 mv of the output voltage, otherwise, the effective power good threshold changes from an absolute threshold to one that tracks the output voltage with a 630 mv offset. the threshold is set differently in different operating modes and the result of the comparison sets the pgood signal. figure 29 , figure 30 and figure 31 show the timing diagram of the pgood signal in different operating modes. the vsns signal is also used by ovp com parator to detect an output over voltage condition. by default, the pgood signal will assert as soon as the vsns signal enters the regulation window. in digital mode, this delay is programmable from 0 to 10ms with a 1 ms resolution, using the mfr_tpgdly co mmand. figure 29 : non - sequence d , non - tracking startup figure 30 : vp tracking ( track_en = 0v) figure 31 : vp sequencing ( track_en =float) over - voltage protection (ovp) over - voltage protection in IR38063 is achieved by comparing sense pin voltage vsns to a configurable overvoltage threshold. for non - track ing operation, in analog mode, or in digital mode using the default configuration, the ovp threshold is set to 0.605v ; for tracking operation , it is set at 1.2*vp. for non - tracking o peration, in digital mode, the ovp threshold may b e reprogrammed to withi n 655 mv of the output voltage (for output voltages lower than 2.555mv, without any resistive divider on the fb pin), using the vout_ov_fault_limit pmbus command . for an ovp threshold programmed to be more than 655 mv greater than the output voltage, the effective ov t hreshold ceases to be an absolute 0 0 0 f a u l t d a c p g d v s n s 0 . 5 v 0 . 4 5 v 0 . 4 2 v 1 6 0 u s 0 r e f e r e n c e d a c 0 . 5 v 0 . 3 v 0 0 0 v p v s n s 0 . 4 v p g d 0 . 9 * v p 1 . 2 * v p 0 0 0 r e f e r e n c e d a c p g d v s n s ( 1 v < v p < 5 v ) 0 . 5 v 0 . 6 0 5 v 0 . 4 5 v 0 v p 0 . 5 v IR38063 35 rev 3.8 may 26 , 2016 value and instead tracks the output voltage with a 655 mv offset. when vsns exceeds the over voltage threshold, an over voltage trip signal asser ts after 200ns (typ.) delay. the default response is that t he h ig h side drive signal hdrv is latched off immediately and pgood flags are set low. the low side drive signal is kept on until the vsns voltage drops below the threshold. hdrv remains latched off until a reset is performed by cycling either vcc or enable, or in the digital mode, using the operation command. IR38063 allows the user to reconfigure this response by the use of the vout_ov_fault_response pmbus command. in addition to the default response described above, this command can be used to configure the device such that vout overvoltage faults are ignored and the converter remains enabled. (however, they will still be flagged in the status_registers and by salert ). for further details on the corresponding pmbus commands related to ovp, please refer to the un0060 ir3806x pmbus commandset user note . vsns voltage is set by an external resistive voltage divider connected to the output. figure 32 : timing diagram for ovp in non - tracking mode minimum on time cons iderations the minimum on time is the shortest amount of time for ctrl fet to b e reliably turned on. this is a very critical parameter for low duty cycle, high frequency applications. in the conventional approach, when the error amplifier output is near the bottom of the ramp waveform with which it is compared to generate the pwm output, propagation delays can be high enough to cause pulse skipping, and hence limit the minimum pulse width that can be realized. moreover, in the conventional approach, the bottom of the ramp often presents a high gain region to the error amplifier output, making the modulator more susceptible to noise and requiring the use of lower control loop bandwidth to pr event noise, jitter and pulse skipping. ir has developed a proprietary scheme to improve and enhance the minimum pulse width which minimizes these delays and hence, allows stable operation with pulse - widths as small as 35ns. at the same time, this scheme also has greater noise immunity, thus allowing stable, jitter free operation down to very low pulse widths even with a high control loop bandwidth, thus reducing the required output capacitance. any design or application using IR38063 must ensure operation with a pulse width that is h igher than the minimum on - time and at least 50 ns of on - time is recommended in the application. this is necessary for the circuit to operate without jitter and pulse - skipping, which can cause high inductor current ripple and hi gh output voltage ripple. ( 2 ) in any application that uses IR38063 , the following condition must be satisfied: ( 3 ) ( 4 ) ( 5 ) the minimum output voltage is limited by the reference voltage and hence v out(min) = 0. 5 v. therefore, for v out(min) = 0. 5 v, s out s on f vin v f d t ? ? ? on on t t ? (min) s in out on f v v t ? ? (min) (min) on out s in t v f v ? ? ? h d r v 0 0 0 l d r v v o u t d a c 1 + o v _ o f f s e t _ d a c c o m p 0 0 p g o o d d a c 1 2 0 0 n s h y s t e r e s i s 2 0 0 n s IR38063 36 rev 3.8 may 26 , 2016 ( 6 ) therefore, at the maximum recommended input voltage 21v and minimum output voltage, the converter should be designed at a switching frequency that does not exceed 476 khz. c onversely, for operation at the maximum recom mended operating frequency (1.5 mhz) an d minimum output voltage (0.5v), t he input voltage (pvin) should not exceed 6.7v , otherwise pulse skipping may happen. maximum duty ratio a certain off - time is specified for IR38063 . this provide s an upper limit on the operating duty ratio at any given switching frequency. the off - time remains at a relatively fixed ratio to switching period in the low a nd mid frequency range, while at higher frequencies, the maximum duty ratio at which IR38063 can operate shows a corresponding decrease . fi gure 33 shows a plot of the maximum duty ratio vs. the switching frequency with built in input voltage feed forward mechanism . fi gure 33 : maximum duty cycle vs. switching frequency (min) on out s in t v f v ? ? ? 05 10 50 . / in s v v f v s ns ? ? ? ? ? IR38063 37 rev 3.8 may 26 , 2016 design example the following example is a typical application for the IR38063. p v in = vin 12v f s = 607 khz v o = 1.2v i o = 25a ripple voltage = 1% * v o v o = 5 % * vo (for 3 0% load transient) digital mode operation enabling the IR38063 as explained earlier, in analog mode, the precise threshold of the enable lends itself well to implementation of a uvlo for the bus voltage as shown in figure 34 . figure 34 : using enable pin for uvlo implementation for a typical enable threshold of v en = 1.2 v ( 7 ) ( 8 ) for p v in (min) =9.2v, r 1 =49.9k and r 2 =7.5k ohm is a good choice. alternatively, if used in digital mode, the pvin uvlo thresholds may be programmed to suitable values such as 9v and 8v, through the vin_on and vin_off pmbus commands or through the appropriate configuration registers respectively. programming the frequency the device is programmed with a default switching frequency=607 khz. this value may be read using the frequency_switch pmbus command. if operating in analog mode, t he timing resistor rt should be chosen to be 3.83k output voltage programming the IR38063 offers flexibility for programming the output voltage. two distinct methods of programming the output voltage are available and the appropriate one should be chosen d epending upon if the mode of operation is analog or digital. in the analog mode of operation, the output voltage is programmed by the reference voltage and an external resistive divider. the fb pin is the inverting input of the error amplifier, which is internally referenced to vref. the divider ratio is set such that the voltage at the vref pin equals that at the fb pin when the output is at its desired value. when an external resistor divider is connected to the output as shown in figure 35 , the output voltage is defined by using the following equation: ( 9 ) ( 10 ) figure 35 : typical application of the ir38 063 for programming the output voltage ho wever, in the digital mode of operation, the vout related pmbus commands and the vout related registers allow the user to program the output voltage directly, by changing the reference voltage (up to a maximum of 2.555v) in response to the commanded r 1 r 2 e n a b l e i r 3 8 0 6 3 v i n 2 (min) 12 1.2 in en r pv v rr ? ? ? ? 21 (min) en in en v rr pv v ? ? ? ? ? ? ? ? ? ? ? ? ? 6 5 1 r r v v ref o ? ? ? ? ? ? ? ? ? ? ? ref o ref v v v r r 5 6 r 5 r 6 f b i r 3 8 0 6 3 v o IR38063 38 rev 3.8 may 26 , 2016 voltage. ther efore, no resistive divider is necessary for this design since vo=1.2v. bootstrap capacitor selection to drive the control fet, it is necessary to supply a gate voltage at least 4v greater than the voltage at the sw pin, which is connected to the source of the control fet. this is achieved by using a bootstrap configuration, which comprises the internal bootstrap diode and an external bootstrap capacitor (c1). the operation of the circuit is as follows: when the sync fet is turned on, the capacitor node co nnected to sw is pulled down to ground. the capacitor charges towards v cc through the internal bootstrap diode ( figure 36 ), which has a forward voltage drop v d . the voltage v c across the bootstrap capacitor c1 is approximately given as: ( 11 ) when the control fet turns on in the next cycle, the capacitor node connected to s w rises to the bus voltage p v in . however, if the value of c1 is appropriately chosen, the voltage v c across c1 remains approximately unchanged and the voltage at the boot pin becomes: ( 12 ) figure 36 : bootstrap circuit to generate vc voltage a bootstrap capacitor of value 0.1uf is suitable for most applications. input capacitor selection the ripple currents generated during the on time of the control fets should be provided by the input capacitor. the rms value of this ripple for each channel is expressed by: ( 13 ) ( 14 ) where: d is the duty cycle i rms is the rms value of the input capacitor current. io is the output current. i o =25a and d = 0.1, the i rms = 7.5a. ceramic capacitors are recommended due to their peak current capabilities. they also feature low esr and esl at higher frequency which enables better efficiency. for this application, it is advisable to have 4 x22uf, 25v ceramic capacitors, c 3216x5r1e226m160ab from tdk . in addition to these, although not mandatory, a 1x330uf, 25v smd capacitor eev - fk1e331p from pan asonic may also be used as a bulk capacitor and is recommended if the input power supply is not located close to the converter. inductor selection inductors are selected based on output power, operating frequency and efficiency requirements. a low indu ctor value causes large ripple current, resulting in the smaller size, faster response to a load transient but poor efficiency and high output noise. generally, the selection of the inductor value can be reduced to the desired maximum ripple current in the inductor ( i ). the optimum point is usually found between 20% and 50% ripple of the output current. for the buck converter, the inductor value for the desired operating ripple current can be determined using the following relation: ( 15 ) where: p v in = maximum input voltage d cc c v v v ? ? boot in cc d v pv v v ? ? ? l v c c 1 p v i n v c c s w + - b o o t p g n d + v d - i r 3 8 0 6 3 c v i n ? ? d d i i o rms ? ? ? ? 1 o in v d pv ? 1 ; in o s i pv v l t d tf ? ? ? ? ? ? ? ? ? ? o in o in s v l pv v pv i f ? ? ? ? ? ? IR38063 39 rev 3.8 may 26 , 2016 v 0 = output voltage i = inductor ripple current f s = switching frequency t = on time for control fet d = duty cycle if i 34 %* i o , then the inductor is calculated to be 0.212 h. select l =0.215 h, pcdc1008 - r215emo, from cyntec which provides a compact, low profile inductor suitable for this application. the selected inductor value give a peak - to - peak inductor ripple current=8.3a. ou tput capacitor selection the voltage ripple and transient requirements determine the output capacitors type and values. the criterion is normally based on the value of the effective series resistance (esr). however the actual capacitance value and the equi valent series inductance (esl) are other contributing components. these components can be described as: ( 16 ) where: v 0 = output voltage ripple i l = inductor ripple current since the output capacitor has a major role in the overall performance of the converter and determines the result of transient response, selection of the capacitor is critical. the IR38063 can perform well with all types of capacitors. as a rule, the capacitor must have low enough esr to meet output ripple and load transient requirements. the goal for this design is to meet the voltage ripple requirement in the smallest possible capacitor size. therefo re it is advisable to select ceramic capacitors due to their low esr and esl and small size. seven of tdk c2012x5r0j476m (47uf/0805/x5r/6.3v) capacitors is a good choice. it is also recommended to use a 0.1f ceramic capacitor at the output for high freq uency filtering. feedback compensation the IR38063, while allowing flexibility and configurability through the digital wrapper of the pmbus interface, still employs a high performance voltage mode control engine. the control loop is a single voltage feed back path including error amplifier and a pwm comparator. to achieve fast transient response and accurate output regulation, a compensation circuit is necessary. the goal of the compensation network is to provide a closed - loop transfer function with the hi ghest 0 db crossing frequency and adequate phase margin (greater than 45 o ). the output lc filter introduces a double pole, - 40db/decade gain slope above its corner resonant frequency, and a total phase lag of 180 o . the resonant frequency of the lc filter is expressed as follows: ( 17 ) figure 37 shows gain and phase of the lc filter. since we already have 180 o phase shift from the output filter alone, the system runs the risk of being unstable. figure 37 : gain and phase of lc filter ? ? ? ? ) ( c o esl o esr o o v v v v ? ? ? ? ? ? ? esr i v l esr ? ? ? ? ) ( 0 0( ) in o esl pv v v esl l ? ?? ? ? ? ?? ?? s o l c f c i v ? ? ? ? ? 8 ) ( 0 o o lc c l f ? ? ? ? ? 2 1 phase 0 0 f lc 0 frequency f lc frequency 0 0 - 180 0 0 db - 40 db / decade - 90 gain IR38063 40 rev 3.8 may 26 , 2016 the IR38063 uses a voltage - type error amplifier with high - gain (90db) and high - bandwidth (30mhz). the output of the amplifier is available for dc gain control and ac phase compensation. the error ampl ifier can be compensated either in type ii or type iii compensation. local feedback with type ii compensation is shown in figure 38 . this method req uires that the output capacitor have enough esr to satisfy stability requirements. if the output capacitors esr generates a zero at 5khz to 50khz, the zero generates acceptable phase margin and the type ii compensator can be used. the esr zero of the outp ut capacitor is expressed as follows: ( 18 ) figure 38 : type ii compensation network and its asymptotic gain plot the transfer function ( v e /v out ) is given by: ( 19 ) the (s) indicates that the transfer function varies as a function of frequency. this configuration introduces a gain and zero, expressed by: ( 20 ) ( 21 ) first select the desired zero - crossover frequency ( f o ): and ( 22 ) use the following equation to calculate r3: ( 23 ) where: p v in = maximum input voltage v osc = effective amplitude of the oscillator ramp f o = crossover frequency f esr = zero frequency of the output capacitor f lc = resonant frequency of the output filter r 5 = feedback resistor to cancel one of the lc filter poles, place the zero before the lc filter resonant frequency pole: ( 24 ) use equation (22), (23) and (24) to calculate c3. one more capacitor is sometimes added in parallel with c3 and r3. this introduces one more pole which is mainly used to suppress the switching noise. the additional pole is given by: ( 25 ) the pole sets to one half of the switching frequency which results in the capacitor c pole : o esr c esr f ? ? ? ? ? 2 1 v out v ref r 6 r 5 c pole c 3 r 3 ve f z f pole e / a z f frequency gain ( db ) h ( s ) db fb comp z in 3 5 3 3 1 ) ( c sr c sr z z s h v v in f out e ? ? ? ? ? ? 5 3 ) ( r r s h ? 3 3 2 1 c r f z ? ? ? ? ? esr o f f ? s o f f ? ? ) 10 / 1 ~ 5 / 1 ( 5 3 2 osc o esr in lc v f f r r pv f ? ? ? ? ? lc z f f ? ? % 75 o o z c l f ? ? ? ? ? 2 1 75 . 0 pole pole p c c c c f ? ? ? ? ? 3 3 2 1 ? IR38063 41 rev 3.8 may 26 , 2016 ( 26 ) for a general unconditional stable solution for any type of output capacitors with a wide range of esr values, we use a local feedback with a type iii compensation network. the typically used compensation network for voltage - mode controller is shown in figure 39 . figure 39 : type iii compensation network and its asymptotic gain plot again, the transfer function is given by: by replacing z in and z f , according to figure 39 , the transfer function can be expressed as: ( 27 ) the compensation network has three poles and two zeros and they are expressed as follows: ( 28 ) ( 29 ) ( 30 ) ( 31 ) ( 32 ) cross over frequency is expressed as: ( 33 ) based on the frequency of the zero generated by the output capacitor and its esr, relative to the crossover frequency, the compensation type can be different. table 5 shows the compensation types for relative location s of the crossover frequency. table 5 : different types of compensators compensator type f esr vs f o typical output capacitor type ii f lc < f esr < f o < f s /2 electrolytic type iii f lc < f o < f esr sp cap, ceramic the higher the crossover frequency is, the potentially faster the load transient response will be. however, the crossover frequency should be low enough to allow attenuation of switching noise. typically, the control loop bandwidth or crossover frequency ( f o ) is selected such that: the dc gain should be large enough to provide high dc - regulation accuracy. the phase margin should be greater than 45 o for overall stability. in this design, we target f o = 75 khz. s s pole f r c f r c ? ? ? ? ? ? ? 3 3 3 1 1 1 ? ? v out v ref r 6 r 5 r 4 c 4 c 2 c 3 r 3 ve f z 1 f z 2 f p 2 f p 3 e / a z f z in frequency gain ( db ) | h ( s ) | db fb comp in f out e z z s h v v ? ? ? ) ( ? ? ? ? ? ? ? ? ? ? 4 4 3 2 3 2 3 3 2 5 5 4 4 3 3 1 1 1 1 ) ( c sr c c c c sr c c sr r r sc c sr s h ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1 ? p f 4 4 2 2 1 c r f p ? ? ? ? 2 3 3 2 3 2 3 3 2 1 2 1 c r c c c c r f p ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 3 3 1 2 1 c r f z ? ? ? ? ? ? 5 4 5 3 4 2 2 1 2 1 r c r r c f z ? ? ? ? ? ? ? ? ? 34 1 2 in o osc o o pv f r c v l c ? ? ? ? ? ?? ? ? s o f f * 1/10 ~ 1/5 ? IR38063 42 rev 3.8 may 26 , 2016 the specifications p v in = 12v v o = 1.2v v osc = 1.357 (this is a function of p vin , duty cycle and switching frequency. infineons supirbuck online design tool can help the user in accounting for this operating point dependency of the effective oscillator ramp amplitude) v ref = 1.2v l o = 0.215 h c o = 7 x 47f, esr3m each it must be noted here that the value of the capacitance used in the compensator design must be the small signal value. for instance, the small signal capacitance of the 47f capacitor used in this design is 34 f at 1. 2 v dc bias and 607 khz frequency. it is this value that must be used for all computations related to the compensation. the small signal value may be obtained from the manufacturers datasheets, design tools or spice models. alternatively, they may also be inferred from measuring the power stage transfer function of the converter and measuring the double pole frequency f lc and using equation ( 22 ) to compute the small signal c o . these result to: f lc = 22.2 khz f esr = 1220 khz f s /2 = 300 khz select crossover frequency f 0 = 75 khz since f lc IR38063 44 rev 3.8 may 26 , 2016 figure 40 : application circuit for a single supply, 12v to 1.2v, 25a point of load converter b o o t v c c / l d o _ o u t f b c o m p s w v o p g o o d p g o o d r t / s y n c p v i n v i n v p v s n s r s + r s o r s - a d d r s c l / o c s e t s d a / i m o n s a l e r t / t m o n p g n d l g n d t r a c k _ e n p 1 v 8 e n / f c c m r 1 4 9 . 9 k c i n = 1 x 3 3 0 u f / 2 5 v + 4 x 2 2 u f / 1 2 0 6 / x 5 r / 1 6 v r 2 7 . 5 k v i n = 1 2 v r 4 1 8 2 c 4 2 . 2 n f r 5 5 . 6 2 k r 3 1 . 2 1 k c 3 2 2 n f c 2 3 9 0 p f c o = 7 x 4 7 u f / 0 8 0 5 / x 5 r / 6 . 3 v l o 0 . 2 1 5 u h r p g 4 . 9 9 k r a d d r 0 c p 1 v 8 = 1 x 2 . 2 u f / 0 6 0 3 / x 5 r / 1 0 v c v c c = 1 x 1 0 u f / 0 8 0 5 / x 5 r / 1 0 v c b o o t = 0 . 1 u f / 0 6 0 3 / x 7 r / 5 0 v IR38063 45 rev 3.8 may 26 , 2016 typical operating waveforms vin = pvin = 12v, vo ut = 1. 2v, iout = 0 - 25 a, room temperature, no air flow figure 44 : operation 00, immediate off, 25a load ch 1 :p vin , ch 2 :v out , ch 3 :p good , ch 4 :enable figure 45 : inductor node at 25a load ch 3 :sw node figure 42 : pv in start up at 25a load ch 1 :p vin , ch 2 :v out , ch 3 :p good ,ch 4 :v cc figure 43 : operation 80,turn on without margining, 25a load ch 1 :p vin , ch 2 :v out , ch 3 :p good , ch 4 :enable figure 46 : output voltage ripple at 25a load ch 2 :v out figure 41 : pv in start up at 25a load ch 1 :p vin , ch 2 :v out , ch 3 :p good , ch 4 :enable IR38063 46 rev 3.8 may 26 , 2016 figure 48 : short - circuit recovery (hiccup) at 25a load ch2:v out , ch3:p good figure 47 : 0 .35v prebias voltage startup at 0a load ch 2 :v out , ch 3 :p good typical operating waveforms vin = pvin = 12v, vout = 1.2v, iout = 0 - 25a, room temperature, no air flow IR38063 47 rev 3.8 may 26 , 2016 typical operating waveforms vin = pvin = 12v, vo ut = 1. 2v, iout = 0 - 25 a, room temperature, no air flow figure 49 : transient response, 2.5a to 10a step (2.5a/us) ch 2 :v out , ch 4 :i out figure 50 : transient response, 17.5a to 25a step (2.5a/us) ch 2 :v out , ch 4 :i out IR38063 48 rev 3.8 may 26 , 2016 typical operating waveforms vin = pvin = 12v, vo ut = 1. 2v, iout = 0 - 25 a, room temperature, no air flow figure 51 : bode plot at 0a load bandwidth = 83.3khz, phase margin = 56.3 o , gain margin = 10.8db figure 52 : bode plot at 25a load bandwidth = 78.7khz, phase margin = 50.8 o , gain margin = 11.3db 1 2 -60 -40 -20 0 20 40 60 -200 -150 -100 -50 0 50 100 150 200 10 3 10 4 10 5 tr1/db tr2/ f/hz tr1: mag(gain) tr2: unwrapped phase(gain) 1 2 -60 -40 -20 0 20 40 60 -200 -150 -100 -50 0 50 100 150 200 10 3 10 4 10 5 tr1/db tr2/ f/hz tr1: mag(gain) tr2: unwrapped phase(gain) IR38063 49 rev 3.8 may 26 , 2016 typical operating waveforms vin = pvin = 12v, vout = 1.2v, iout = 0 - 25a, room temperature, no air flow figure 54 : power loss versus load current figure 53 : efficiency versus load current IR38063 50 rev 3.8 may 26 , 2016 typical operating waveforms vin = pvin = 12v, vout = 1.2v, iout = 0 - 25a, room temperature, no air flo w figure 55 : thermal image of the board at 25a load IR38063: 72.9 o c, inductor: 58.4 o c, ambient:26.5 o c IR38063 51 rev 3.8 may 26 , 2016 figure 56 : pmbus command summary for the 1.2v design IR38063 52 rev 3.8 may 26 , 2016 i2c protocols all registers may be accessed using either i2c or pmbus protocols. i2c allows the use of a simple format whereas pmbus provides error checking capability. figure 57 shows the i2c format employed by manhattan figure 57 : i2c format smbus/pmbus protocol s to access irs configuration and monitoring registers, 4 different protocols are required: the smbus read/write byte/word protocol with/without pec (for status and monitoring) the smbus send byte protocol with/without pec (for clear_faults only) the smbus block read protocol for accessing model and revision information the smbus process call (for accessi ng configuration registers) in addition, manhattan supports: alert response address (ara) bus timeout (10ms) group command for writing to many vrs within one command figure 58 : smbus write byte/word a a s s l a v e a d d r e s s w r e g i s t e r a d d r e s s d a t a b y t e 1 7 1 8 s 1 7 w 1 a p 8 1 1 1 1 8 w r i t e r e a d p 1 1 s 1 7 r 1 8 n p 1 1 s : s t a r t c o n d i t i o n a : a c k n o w l e d g e ( 0 ' ) n : n o t a c k n o w l e d g e ( 1 ' ) s r : r e p e a t e d s t a r t c o n d i t i o n p : s t o p c o n d i t i o n r : r e a d ( 1 ' ) w : w r i t e ( 0 ' ) p e c : p a c k e t e r r o r c h e c k i n g * : p r e s e n t i f p e c i s e n a b l e d : m a s t e r t o s l a v e : s l a v e t o m a s t e r a a r e g i s t e r a d d r e s s a s l a v e a d d r e s s s l a v e a d d r e s s d a t a b y t e s s l a v e a d d r e s s w c o m m a n d c o d e d a t a b y t e 1 7 1 8 s 1 s l a v e a d d r e s s 7 w 1 a a a a p 8 1 1 1 1 c o m m a n d c o d e d a t a b y t e h i g h 8 a 8 1 d a t a b y t e l o w a 8 1 p e c * 8 1 a * a p 1 1 p e c * 8 1 a * b y t e w o r d s : s t a r t c o n d i t i o n a : a c k n o w l e d g e ( 0 ' ) n : n o t a c k n o w l e d g e ( 1 ' ) s r : r e p e a t e d s t a r t c o n d i t i o n p : s t o p c o n d i t i o n r : r e a d ( 1 ' ) w : w r i t e ( 0 ' ) p e c : p a c k e t e r r o r c h e c k i n g * : p r e s e n t i f p e c i s e n a b l e d : m a s t e r t o s l a v e : s l a v e t o m a s t e r IR38063 53 rev 3.8 may 26 , 2016 figure 59 : smbus read byte/word figure 60 : smbus send byte figure 61 : smbus block read with byte count=1 figure 62 : mfr specific command to write a n ir r egister p s r 7 r 8 d a t a b y t e s s l a v e a d d r e s s w c o m m a n d c o d e 1 7 1 8 a n a a 1 1 1 1 1 1 1 p n d a t a b y t e l o w 1 1 d a t a b y t e h i g h 8 s r 7 r s w 1 7 1 8 a a a 1 1 1 1 1 8 p e c * 8 a * 1 1 p e c * 8 a * 1 b y t e w o r d s l a v e a d d r e s s s l a v e a d d r e s s c o m m a n d c o d e s l a v e a d d r e s s a p p e c * 8 s s l a v e a d d r e s s w c o m m a n d c o d e 1 7 1 8 a a * a 1 1 1 1 a 1 s s l a v e a d d r e s s w c o m m a n d c o d e 1 7 1 8 a a 1 1 b y t e c o u n t = 1 d a t a b y t e 8 s r r 1 7 1 a 1 8 p n 1 1 a * 1 p e c * 8 s l a v e a d d r e s s s p m b u s a d d r e s s w c o m m a n d d 1 h r e g i s t e r a d d r e s s d a t a b y t e a a a a p p e c * a IR38063 54 rev 3.8 may 26 , 2016 figure 63 : smbus custom process call to read a n ir r egister figure 64 : group command a 1 a h i g h d a t a b y t e a a a w a l o w d a t a b y t e a a w a a a a 8 8 s w 1 7 1 8 1 1 1 1 8 p e c 1 * 1 h i g h d a t a b y t e 1 o r m o r e b y t e s 8 8 s r c o m m a n d c o d e 2 1 7 1 8 1 1 1 1 a 8 p e c 2 * 1 a * 1 o r m o r e b y t e s 8 8 s r 1 7 1 8 1 1 1 1 8 p e c n * 1 o r m o r e b y t e s p 1 a * l o w d a t a b y t e s l a v e a d d r e s s 1 s l a v e a d d r e s s 2 c o m m a n d c o d e 1 h i g h d a t a b y t e s l a v e a d d r e s s n c o m m a n d c o d e n l o w d a t a b y t e IR38063 55 rev 3.8 may 26 , 2016 layout recommendations the layout is very important when designing high frequency switching converters. layout will affect noise pickup and can cause a good design to perform with less than expected results. make the connections for the power components in the top layer with wide, copper filled areas or polygons. in general, it is desirable to make proper use of power planes and polygons for power distribution and he at dissipation. the input capacitors, inductor, output capacitors and the IR38063 should be as close to each other as possible . this helps to reduce the emi radiated by the power traces due to the high switching currents through them. place the input capac itor directly at the pvin pin of IR38063 . the feedback part of the system should be kept away from the inductor and other noise sources. the critical bypass component s such as capacitors for vin, vcc and 1.8v should be close to their respective pins. it i s important to place the feedback components including feedback resistors and compensation components close to fb and comp pins. in a multilayer pcb use one layer as a power ground plane and have a control circuit ground (analog ground), to which all signa ls are referenced. the goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function s . these two grounds must be connected together on the pc board layout at a single point. it is recom mended to place all the compensation parts over the analog ground plane in top layer. the power qfn is a thermally enhanced package. based on thermal performance it is recommended to use at least a 6 - layers pcb. to effectively remove heat from the device t he exposed pad should be connected to the ground plane using vias. IR38063 has 3 pins, scl, sda and salert that are used for i2c/pmbus communication. it is recommended that the traces used for these communication lines be at least 10 m ils wide with a spacing between the scl and sda traces that is at least 2 - 3 times the trace width. IR38063 56 rev 3.8 may 26 , 2016 supported pmbus comm ands comma nd code command name smbus transactio n no. of bytes range resoluti on default value description 01h operation r/w byte 1 enables or disables the device and controls margining 02h on_off_config r/w byte 1 configures the combination of enable pin input and serial bus commands needed to turn the unit on and off. 03h clear_faults send byte 0 clear contents of fault registers 10h write_protect r/w byte 1 used to control writing to the pmbus device. the intent of this command is to provide protection against accidental changes. 15h store_user_all send byte 0 burns the user section registers into otp memory 16h restore_user_all send byte 0 copies the otp registers into user memory 19h capability read byte 1 returns 1011 xxxx to indicate packet error checking is supported, m aximum bus speed is 400khz and smbalert# is supported. 1bh smbalert_mask write word/block read process call 2 may be used to prevent a warning or fault condition from asserting the smbalert# signal. 21h vout_command 1 6 r/w word 2 0 - 2.555v/v s 5mv /v s 0.5v causes the device to set its output voltage to the commanded value . v s = vout_scale_loop 22h vout_trim 1 6 r/w word 2 - 128 - +128v 0v available to the device user to trim the output voltage 24h vout_max 1 6 r/w word 2 6v sets an upper limit on the output voltage the unit can command regardless of any other commands or combinations. 25h vout_margin_high 1 6 r/w word 2 0 - 2.555v/v s 5mv /v s 0.55v sets the margin high voltage when commanded by operation v s = vout_scale_loop 26h vout_margin_low 1 6 r/w word 2 0 - 2.555v/v s 5mv /v s 0.45v sets the margin low voltage when commanded by operation v l = vout_scale_loop 27h vout_transition_rate 11 r/w word 2 0 - 127 ms/us 0.125mv /us sets the rate in mv/s at which the output should change voltage. exponent 0 to - 4 allowed. 29h vout_scale_loop 1 1 r/w word 2 0.125 - 1 1 compensates for external resistor divider in feedback path and in the sense path . values 1, 0.5, 0.25, 0.125 allowed. exponent - 3 allowed. 33h frequency_switch 11 r/w word 2 166 - 1500khz 607 khz sets the switch ing frequency, in khz . exponent 0 to 1 allowed. 35h vin_on 11 r/w word 2 0 - 16.5v 0.5v 1v sets the value of the input voltage, in volts, at which the unit should start power conversion. exponent - 1 allowed. 36h vin_off 11 r/w word 2 0 - 16v 0.5v 0.5v sets the value of the input voltage, in volts, at which the unit, once operation has started, should stop power conversion. exponent - 1 allowed. 39h iout_cal_offset 11 r/w word 2 - 128a - +127.5a 0.5a 0a used to null out any offsets in the output current sensing circuit. exponent - 1 allowed. 40h vout_ov_fault_limit 1 6 r/w word 2 (25 - 655mv)/v s 10mv/v s 0.605 v sets the value of the output voltage measured at the sense pin that causes an output overvoltage fault. v s = vout_scale_loop 41h vout_ov_fault_respons e r/w byte 1 ignore/shut down shutdow n instructs the device on what action to take in response to an output overvoltage fault. 42h vout_ov_warn_limit 1 6 r/w word 2 3.9mv 0.56v sets the value of the output voltage at the sense pin that causes an output voltage high warning. 43h vout_uv_warn_limit 1 6 r/w word 2 3.9mv 0.44 v sets the value of the output voltage at the sense pin that causes an output voltage low warning. IR38063 57 rev 3.8 may 26 , 2016 44h vout_uv_fault_limit 1 6 r/w word 2 3.9mv 0.395 v sets the value of the output voltage at the sense pin that causes an output undervoltage fault. 45h vout_uv_fault_respons e r/w byte 1 ignore/shut down ignore instructs the device on what action to take in response to an output undervoltage fault. 46h iout_oc_fault_limit 11 r/w word 2 3 - 37.5 a 0.5a 33 a sets the value of the output current, in amperes, that causes the overcurrent detector to indicat e an overcurrent fault . exponent - 1 allowed. 47h iout_oc_fault_response r/w byte 1 hiccup forever instructs the device on what action to take in response to an output overcurrent fault. 4ah iout_oc_warn_limit 11 r/w word 2 0 - 63.5a 0.5a 28 a sets the value of the output current, in amperes, that causes the overcurrent detector to indicate an overcurrent warning . exponent - 1 allowed. 4fh ot_fault_limit 11 r/w word 2 0 - 150 c 1 c 145 c set the temperature, in degrees celsius, of the unit at which it should indicate an overtemperature fault . exponent 0 allowed. 50h ot_fault_response r/w byte 1 ignore/shut down/inhibi it inhibit instructs the device on what action to take in response to an overtemperature fault. 51h ot_warn_limit 11 r/w word 2 0 - 150 c 1 c 125 c set the temperature, in degrees celsius, of the unit at which it should indicate an overtemperature warning alarm. exponent 0 allowed. 55h vin_ov_fault_limit 11 r/w word 2 6.25v - 24v 0.25v 24v sets the value of the input voltage that causes an input overvoltage fault. exponent - 2 allowed. 56h vin_ov_fault_response r/w byte 1 ignore/shut down shutdow n instructs the device on what action to take in response to an input overvoltage fault. 58h vin_uv_warn_limit 11 r/w word 2 0 - 16v 0.5v 0.5v sets the value of the input voltage pvin, in volts, that causes an input overvoltage fault. exponent - 1 allowed. 5eh power_good_on 16 r/w word 2 (0 - 0.63v)/v s 10mv /v s 0.45v sets the output voltage at which an optional power_good signal should be asserted. v s =vout_scale_loop 5fh power_good_off 1 6 r/w word 2 (0 - 0.63v)/v s 10mv /v s 0.42v sets the output voltage at which an optional power_good signal should be negated. v s =vout_scale_loop 60h ton_delay 11 r/w word 2 0 - 127ms 1ms 0ms sets the time, in milliseconds, from when a start condition is received (as programmed by the on_off_config command) until the output voltage starts to rise. exponent 0 allowed. 61h ton_rise 11 r/w word 2 0 - 127ms 1ms 2 ms sets the time, in milliseconds, from when the output starts to rise until the voltage has entered the regulation band. exponent 0 allowed. 62h ton_max_fault_limit 11 r/w word 2 0 - 127ms 1ms 0 (no limit) sets an upper limit, in milliseconds, on how long the unit can attempt to power up the output without reaching the output undervoltage fault limit . exponent 0 allowed. 63h ton_max_fault_respons e r/w byte 1 ignore/shut down ignore instructs the device on what action to take in response to a ton_max fault. 64h toff_delay r/w word 2 0 - 127ms 1ms 0ms sets the time, in milliseconds, from a stop condition is received (as programmed by the on_off_config command) until the unit stops transferring energy to the output. exponent 0 allowed. 65h toff_fall r/w word 2 0 - 127ms 1ms 1 ms device will acknowledge this command but ignore it. 78h status byte read byte 1 returns 1 byte where the bit meanings are: bit <7> device busy fault bit <6> output off (due to fault or enable) bit <5> output over - voltage fault bit <4> output over - current fault bit <3> input under - voltage fault bit <2> temperature fault IR38063 58 rev 3.8 may 26 , 2016 bit <1> communication/memory/logic fault bit <0>: none of the above 79h status word read word 2 returns 2 bytes where the low byte is the same as the status_byte data. the high byte has bit meanings are: bit <7> output high or low fault bit <6> output over - current fault bit <5> input under - voltage fault bit <4> reserved; hardcoded to 0 bit <3> output power not good bit <2:0> hardcoded to 0 7ah status_vout read byte 1 reports types of vout related faults. 7bh status_iout read byte 1 reports types of iout related faults. 7ch status_input read byte 1 reports types of input related faults. 7dh status_temperature read byte 1 returns over temperature warning and over temperature fault (otp level). does not report under temperature warning/fault. the bit meanings are: bit <7> over temperature fault bit <6> over temperature warning bit <5> under temperature warning bit <4> under temperature fault bit <3:0> reserved 7eh status_cml read byte 1 returns 1 byte where the bit meanings are: bit <7> command not supported bit <6> invalid data bit <5> pec fault bit <4> otp fault bit <3 :2> reserved bit<1> other communication fault bit<0> other memory or logic fault; hardcoded to 0 88h read_vin 11 read word 2 re turns the input voltage in volts 8bh read_vout 1 6 read word 2 returns the output voltage in volts 8ch read_iout 11 read word 2 return s the output current in amperes 8dh read_temperature 11 read word 2 returns the device temperature in degrees celcius 96h read_pout 11 read word 2 r eturns the output power in watts 98h pmbus_revision read byte 1 rep orts pmbus part i rev 1.1 & pmbu s part ii rev 1.2(draft) 99h mfr_id block read/write 3 ir returns 2 bytes u se d to read the manufacturers id. user can overwrite with any value. 9ah mfr_model block read/write 2 set 00 if set to 00h, r eturns a 1 byte code corresponding to ic_device_id. alternatively, user can set to any non - zero value 9bh mfr_revision block read/write 2 set 00 if set to 00h, r eturns a 1 byte code corresponding to ic_device_rev. alternatively, user can set to any non - zero value adh ic_device_id block read 2 used to read the type or part number of an ic. ir38060: 30h ir38061:31h ir38060 : 32h ir38060 : 33h ir38064:34h ir38065:35h IR38063 59 rev 3.8 may 26 , 2016 aeh ic_device_rev block read 2 used to read the revision of the ic d0h mfr_read_reg custom 2 manufacturer specific: read from configuration registers d1h mfr_write_reg custom 2 manufacturer specific: write to configuration & status registers d8h mfr_tpgdly r/w word 2 0 - 10ms 1ms 0ms sets the delay in ms, between the output voltage entering the regulation window and the assertion of the pgood signal . exponent 0 allowed. d9h mfr_fccm r/w byte 1 0 - 1 1 (ccm) allows the user to choose between forced continuous conduction mode and adaptive on - time operation at light load. d6h mfr_i2c_address r/w word 1 0 - 7fh 10h sets and returns the device i2c base address dbh mfr_vout_peak 1 6 read word 2 continuously records and reports the highest value of read vout. dch mfr_iout_peak 11 read word 2 continuously records and reports the highest value of read iout. ddh mfr_temperature_peak 11 read word 2 continuously records and reports the highest value of read_temperature IR38063 60 rev 3.8 may 26 , 2016 pcb pads and compone nt p cb copper and solder resist (pad sizes) IR38063 61 rev 3.8 may 26 , 2016 pcb copper and solde r resist (pad spacin g) IR38063 62 rev 3.8 may 26 , 2016 solder paste stencil (pad sizes) solder paste stencil (pad spacing) IR38063 63 rev 3.8 may 26 , 2016 marking information tape and reel information refer to application note an - 1132 for more information. irxxxx irxxxx IR38063 64 rev 3.8 may 26 , 2016 package information 34 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 10 9 8 7 6 5 4 3 2 1 11 side view ( back ) 33 side view ( front ) top view side view ( left ) side view ( right ) pin 1 a b c IR38063 65 rev 3.8 may 26 , 2016 bottom view dimension table symbol minimum nominal maximum a 0 . 80 0 . 90 1 . 00 a 1 0 . 00 0 . 02 0 . 05 a 3 0 . 203 ref b 1 0 . 45 0 . 50 0 . 55 b 2 0 . 30 0 . 35 0 . 40 b 3 0 . 20 0 . 25 0 . 30 b 4 0 . 325 0 . 375 0 . 425 d 5 . 00 bsc e 7 . 00 bsc d 1 3 . 450 3 . 500 3 . 550 e 1 1 . 725 1 . 775 1 . 825 d 2 0 . 725 0 . 775 0 . 825 e 2 1 . 292 1 . 342 1 . 392 d 3 1 . 823 1 . 873 1 . 923 e 3 1 . 932 1 . 982 2 . 032 l 1 0 . 35 0 . 40 0 . 45 l 2 0 . 822 0 . 872 0 . 922 e 1 0 . 500 bsc e 2 0 . 625 bsc e 3 1 . 125 bsc e 4 1 . 250 bsc e 5 0 . 925 bsc e 6 1 . 373 bsc e 7 0 . 825 bsc e 8 0 . 750 bsc aaa 0 . 05 bbb 0 . 10 ccc 0 . 10 ddd 0 . 05 eee 0 . 08 n 34 10 18 19 30 31 34 1 9 1 9 18 10 19 30 31 34 pin 1 ( r 0 . 20 ) IR38063 66 rev 3.8 may 26 , 2016 environmental qualif ications qualification level industrial moisture sensitivity level 5mm x 7mm pqfn msl2 esd machine model (jesd22 - a115a) jedec class b human body model (jesd22 - a114f) jedec class 2 (2 kv) charged device model (jesd22 - c101d) jedec class 3 rohs compliant yes ( with exemption 7a ) ? qualification standards can be found at international rectifier web site: http://www.irf.com IR38063 67 rev 3.8 may 26 , 2016 rev i sion history rev. date description 3.0 9/9/2015 initial dr3 release 3.1 10/5/2015 corrected oc test condition 3.2 10/17/2015 recommended vcc range, corrected typos updated frequency_switch default to 607khz (was 600khz) 3.3 10/21/2015 added reference to un0060 pmbus commandset corrected default ton_rise to 2ms (was 1ms) 3.4 11 / 06 /2015 added reference accuracy over - 40c ? +125c updated package drawing to include l - shaped pin 3.5 1/15/2016 improved assembly drawing quality removed unnecessary info from marking diagram added linear telemetry formats to pmbus command table corrected mfr_id/model/rev and other descriptions in pmbus command table clearly specified vin/vcc operating ranges added tape & reel information converted to infineon format 3.6 1/25/2016 added ac specification for boot to sw , explicitly stated that no rt resistor needed in digital mode, corrected a typo in vin operating range to pvin operating range 3.7 3/4/2016 corrected iout_oc_fault_limit , iout_oc_fault_response and iout_oc_warn_limit range and defaults in pmbus commandset table 3.8 5/26/2016 changed vcc recommended limits, changed iout reporting resolution display format from 0.0625a to 62.5 ma IR38063 68 rev 3.8 may 26 , 2016 published by infineon technologies ag 81726 mnchen, germany ? infineon technologies ag 2015 all rights reserved. important notice the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (beschaffenheitsgarantie). with respect to any examples, hints or any typical values stated herein and/or any information regarding the a pplication of the product , infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non - infringement of intellectual property rights of any third party. in addition , any informa tion given in this document is subject to customer s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customers products and any use of the product of infineon technologies in cu stomers applications. the data contained in this document is exclusively intended for technically trained staff. it is the responsibility of customers technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. for further information on the product, technology, delivery terms and conditions and prices please contact your nearest infineon technologies o ffice ( www.infineon.com ). warnings due to technical requirements products may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies o ffice. except as other wise explicitly approved by infineon technologies in a written document signed by authorized representatives of infineon technologies, infineon technologies products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury. |
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